OpenOpportunity Sourced Jobs — Hyderabad
Full Time · On Site · Entry Level
Role: Design Verification Engineer | Department: Engineering - Hardware & Networks | Industry: Electronic Components / Semiconductors | Education: UG: Any Graduate PG: Any Postgraduate Define and develop verification environments Write verification plans, and documentation Generate test bench and automatic regression plans Be responsible for verification architecture, simulations, verifications, and debugging of circuit and logic designs Complete block-level verification and chip level verification Bring a self-motivated and enthusiastic approach that will achieve any new requirements and overcome all challenges Able to work mostly independently and handle complex SoC Verification platform. Able to debug the RTL for design intent and Interface with cross-functional teams and collaboration in all verification related activities Requirements/Qualifications: Minimum of 8 years related proven silicon design or verification work experience Hands on project experience with leading edge verification methodologies like OVM/UVM One of the Protocol knowledge areas AXI/AHB/DDR/PCIe is must Hands on project experience in coverage/assertion driven verification Note: The listing's own Requirements section states "Minimum of 8 years related proven silicon design or verification work experience" for a role titled "Principal Engineer, Verification" - directly contradicting the structured Experience field ("0 - 2 years") and its surfacing in a search filtered to 0-2 years. This is a stark title/seniority mismatch: a Principal-level position with an explicit 8-year bar appearing alongside listings meant for freshers and early-career candidates.
VHDL, Simulation, Chip design, Analytical, Circuit designing, CAD, Perl, System verilog, UVM, Recruitment