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Role: Technical Architect | Department: Engineering - Software & QA | Industry: IT Services & Consulting | Education: UG: Any Graduate; PG: Any Postgraduate Define the AI architecture strategy spanning data pipelines, model selection, and deployment for semiconductor design use cases. Architect and prototype AI/ML solutions that augment backend design, STA, DFT, and physical verification flows (e.g., PPA optimization, automated DFT insertion, log/report analysis, predictive timing closure). Integrate LLMs and ML models into existing EDA toolchains (Innovus, Tempus, PrimeTime, Calibre, etc.) and Linux/TCL/Python scripting environments. Architect agentic AI workflows — agents that plan, execute, and iterate across multistep design tasks (debug triage, ECO loop automation, constraint generation, regression analysis) with appropriate human-in-the-loop checkpoints. Design multi-agent systems that orchestrate specialized agents across the RTL-to-GDSII flow, integrating tool calls to EDA engines, scripts, and internal knowledge bases. Build robust agent infrastructure — tool/function-calling interfaces, context and memory management, state handling, and guardrails for reliability in engineering-critical applications. Evaluate and benchmark foundation models, fine-tuning approaches, RAG pipelines, and agent orchestration patterns. Establish an agent control plane — policy approval gates, observability, and audit trails — before autonomous agents touch production systems. Partner with delivery teams and clients to translate AI capabilities into productized service offerings. Establish MLOps practices, model governance, and scalable infrastructure (on-prem/cloud/hybrid). Mentor engineers on AI/ML adoption and build the technical foundation for an AI Center of Excellence. Experience (years): 10+ years Education Qualification: B.Tech/M.Tech in Electrical/Electronics/Computer Science Engineering or Equivalent. Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying. Note: This role is well-tagged and internally consistent — it genuinely blends AI/ML architecture with a semiconductor backend-design domain (EDA toolchains, RTL-to-GDSII flow), and the Role tag "Technical Architect" fits the content. The source text itself shows some run-together words without spaces in places (e.g., "multistep," "onpremcloudhybrid"), which appears to be a formatting artifact from how the original posting's bullet points were transcribed rather than a content issue. Originally posted on Naukri: https://www.naukri.com/job-listings-ai-architect-chip-design-semiconductor-background-mirafra-software-technologies-pvt-ltd-bengaluru-10-to-15-years-060826502469
MLOps, Debug, EDA, Orchestration, Data Pipelines, PrimeTime, AI, Innovus, Prototype, Physical Verification, Memory Management, Automation, DFT, RAG Pipelines, Regression, RAG, Observability, ML Models, Architecture, Chip Design, Deployment, ML