OpenOpportunity Sourced Jobs — Bengaluru
Full Time · On Site · Entry Level
Role: Functional Verification Engineer | Department: Engineering - Hardware & Networks | Industry: Engineering & Construction | Education: UG: Any Graduate PG: Any Postgraduate Responsibilities Work as part of a dynamic, motivated, hardworking team Leading the verification team delivering end to end verification, handling block and full-chip verification of complex SoCs Your responsibilities may include Verification environment development, Test cases development, Function and code Coverage Analysis, software integration, etc. You may also work on Verification IP development or IP Verification activities Required Skills Strong technical fundamentals with superior analytical and problem solving skills, familiarity with OOPs and scripting languages Very strong proficiency in HVLs and HDLs (SystemVerilog, Verilog, VHDL, etc.) Prior expertise with OVM/UVM based test bench with assertion is a big plus. Working experience in functional coverage and constrained random testing Expertise in verification of protocols like Ethernet, PCIe, SATA, USB, SAS, DDR, etc. ARM based SoC verification is a big plus Good communication skills, both written and oral Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying. Note: A third distinct meaning of "SAS" surfaces here -- a hardware storage-interface protocol, Serial Attached SCSI, listed alongside Ethernet, PCIe, SATA and USB in a chip-verification engineer's protocol checklist, with zero connection to the SAS statistical software. Combined with SHF Design Engineering's and Hitachi Energy's listings (Substation Automation System) and SAS Sales Group's company-name coincidence, this single search surfaces four unrelated meanings of the same three-letter acronym.
VHDL, SAS, USB, Analytical, Verilog, Ethernet, PCIE, Test cases, SATA, UVM