OpenOpportunity Sourced Jobs — Chennai
Full Time · On Site · Entry Level
Role: Design Engineer | Department: Production, Manufacturing & Engineering | Industry: Industrial Equipment / Machinery | Education: UG: Any Graduate PG: Any Postgraduate Job Details Qualification: Fresh Graduate, Diploma in Designing, Digital Imaging software Skills: Knowledge in CAD CAM Designing / Artistic Experience: 0 to 6 months in Digital Designing preferable Employment Type: Full Time Gender: M/F Location: Chennai - US Shift Job Category: Production Job Location: Chennai - US Shift Disclaimer: This job description has been sourced from a public domain and may have been modified by Naukri.com to improve clarity for our users. We encourage job seekers to verify all details directly with the employer via their official channels before applying. Note: This is a genuine dental-prosthetics CAD/CAM design role at a dental lab (working US shift hours to serve US-based dental clients), with zero connection to semiconductor or VLSI design. Yet its scraped Key Skills list is saturated with VLSI/ASIC chip-design terminology entirely unrelated to dentistry -- "asic verification," "vlsi design," "uvm," "vhdl," "verilog," "asic design," "rtl design," "rtl coding," "system verilog," "fpga" -- the most extreme skill-tag cross-contamination case found across this entire project, as though an entire semiconductor job's tag set was merged onto this listing. The posting also carries its own aggregator disclaimer ("sourced from a public domain and may have been modified by Naukri.com"), a differently worded variant of the "aggregated from external source" boilerplate seen on other listings in this project, confirming Naukri runs more than one third-party content-aggregation pipeline with different disclaimer templates.
digital, asic verification, vlsi design, c, production, cad, digital design, uvm, vhdl, design engineering, autocad, cam, verilog, asic design, catia, rtl design, fpga, solid works, cad cam, fpga design, design, rtl coding, vlsi, system verilog